Amin-Javaheri, Masoud; Orin, David E. Systolic architectures for the manipulator inertia matrix. (English) Zbl 0668.93053 IEEE Trans. Syst. Man Cybern. 18, No. 6, 939-951 (1988). Systolic architectures consisting of 1, N, and \(N(N+1)/2\) processors are presented for computing the manipulator inertia matrix. A VLSI-based robotics processor, which is under development, is the fundamental component of the architecture. Its major elements are a 32-bit floating- point multiplier, 32-bit floating-point adder, triple-port memory, and four I/O ports for external communication which are interconnected to facilitate implementation of robotics operations. The algorithm used is based on recursive computation of the inertial parameters of sets of composite rigid bodies and is programmed to exploit any inherent parallelism. Good results are obtained for the N-processor and \(N(N+1)/2\)-processor configurations that give a compute time delay that is of O(N). In addition, I/O time and idle time due to processor synchronization as well as CPU utilization and on-chip memory size are fully included in the evaluation and indicate the feasibility and effectiveness of the design. Cited in 1 Document MSC: 93C95 Application models in control theory 93B50 Synthesis problems 93B40 Computational methods in systems theory (MSC2010) 70Q05 Control of mechanical systems 68N99 Theory of software 68N25 Theory of operating systems Keywords:Systolic architectures; manipulator inertia matrix; VLSI-based robotics processor; robotics operations; inertial parameters; rigid bodies; CPU utilization PDFBibTeX XMLCite \textit{M. Amin-Javaheri} and \textit{D. E. Orin}, IEEE Trans. Syst. Man Cybern. 18, No. 6, 939--951 (1988; Zbl 0668.93053) Full Text: DOI