Serrano-Cases, Alejandro; Reina, Juan M.; Abella, Jaume; Mezzetti, Enrico; Cazorla, Francisco J. Leveraging hardware QoS to control contention in the Xilinx Zynq Ultrascale+ MPSoC. (English) Zbl 07699452 Brandenburg, Björn B. (ed.), 33rd Euromicro conference on real-time systems, ECRTS 2021, virtual conference, July 5–9, 2021. Wadern: Schloss Dagstuhl – Leibniz-Zentrum für Informatik. LIPIcs – Leibniz Int. Proc. Inform. 196, Article 3, 26 p. (2021). MSC: 68M20 PDFBibTeX XMLCite \textit{A. Serrano-Cases} et al., LIPIcs -- Leibniz Int. Proc. Inform. 196, Article 3, 26 p. (2021; Zbl 07699452) Full Text: DOI
Zhang, Hui; Wu, Jinzhao Formal verification and quantitative metrics of MPSoC data dynamics. (English) Zbl 1382.68145 Formal Asp. Comput. 30, No. 2, 219-237 (2018). MSC: 68Q60 68Q45 PDFBibTeX XMLCite \textit{H. Zhang} and \textit{J. Wu}, Formal Asp. Comput. 30, No. 2, 219--237 (2018; Zbl 1382.68145) Full Text: DOI
Mohaqeqi, Morteza; Kargahi, Mehdi Utility accrual object distribution in MPSoC real-time embedded systems. (English) Zbl 1264.68031 J. Comput. Syst. Sci. 79, No. 4, 406-420 (2013). MSC: 68M14 68M20 PDFBibTeX XMLCite \textit{M. Mohaqeqi} and \textit{M. Kargahi}, J. Comput. Syst. Sci. 79, No. 4, 406--420 (2013; Zbl 1264.68031) Full Text: DOI
Liu, Tiantian; Zhao, Yingchao; Li, Minming; Xue, Chun Jason Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC. (English) Zbl 1225.68051 J. Parallel Distrib. Comput. 71, No. 11, 1473-1483 (2011). MSC: 68M15 68M14 PDFBibTeX XMLCite \textit{T. Liu} et al., J. Parallel Distrib. Comput. 71, No. 11, 1473--1483 (2011; Zbl 1225.68051) Full Text: DOI
Lombardi, Michele; Milano, Michela; Ruggiero, Martino; Benini, Luca Stochastic allocation and scheduling for conditional task graphs in multi-processor systems-on-chip. (English) Zbl 1232.68017 J. Sched. 13, No. 4, 315-345 (2010). MSC: 68M07 68M20 05C90 PDFBibTeX XMLCite \textit{M. Lombardi} et al., J. Sched. 13, No. 4, 315--345 (2010; Zbl 1232.68017) Full Text: DOI
Huang, Qing-quan; Hong, Sha; Wu, Yuan-fu Analysis of data queue in multiprocessor system-on-chip at transaction level. (Chinese. English summary) Zbl 1173.68407 J. Comput. Appl. 28, No. 4, 1049-1051 (2008). MSC: 68M20 PDFBibTeX XMLCite \textit{Q.-q. Huang} et al., J. Comput. Appl. 28, No. 4, 1049--1051 (2008; Zbl 1173.68407) Full Text: DOI
Kriaa, Lobna; Bouchhima, Aimen; Gligor, Marius; Fouillart, Anne-Marie; Pétrot, Fréderic; Jerraya, Ahmed-Amine Parallel programming of multi-processor soC: A HW-SW interface perspective. (English) Zbl 1135.68364 Int. J. Parallel Program. 36, No. 1, 68-92 (2008). MSC: 68N19 PDFBibTeX XMLCite \textit{L. Kriaa} et al., Int. J. Parallel Program. 36, No. 1, 68--92 (2008; Zbl 1135.68364) Full Text: DOI
Issenin, Ilya; Dutt, Nikil Using FORAY models to enable MPSoC memory optimizations. (English) Zbl 1135.68322 Int. J. Parallel Program. 36, No. 1, 93-113 (2008). MSC: 68M10 68M99 PDFBibTeX XMLCite \textit{I. Issenin} and \textit{N. Dutt}, Int. J. Parallel Program. 36, No. 1, 93--113 (2008; Zbl 1135.68322) Full Text: DOI
Zitouni, Abdelkrim; Tourki, Rached Arbiter synthesis approach for SoC multi-processor systems. (English) Zbl 1129.68406 Comput. Electr. Eng. 34, No. 1, 63-77 (2008). MSC: 68M99 PDFBibTeX XMLCite \textit{A. Zitouni} and \textit{R. Tourki}, Comput. Electr. Eng. 34, No. 1, 63--77 (2008; Zbl 1129.68406) Full Text: DOI