Li, Szu-Ju; Dai, Jing-Fu; Chang, Chia-Cherng; Huang, Chau-Hsin; Tsai, Yao-Tsung Development of 3-D equivalent-circuit modelling with decoupled L-ILU factorization in semiconductor-device simulation. (English) Zbl 1119.82041 Int. J. Numer. Model. 20, No. 3, 133-148 (2007). Reviewer: Andreas Knorr (Berlin) MSC: 82D37 94C30 PDFBibTeX XMLCite \textit{S.-J. Li} et al., Int. J. Numer. Model. 20, No. 3, 133--148 (2007; Zbl 1119.82041) Full Text: DOI
Li, Szu-Ju; Ho, Chi-Hon; Tsai, Yao-Tsung Kronig-Penney model simulation with equivalent circuit method. (English) Zbl 1241.82013 Int. J. Numer. Model. 20, No. 3, 109-116 (2007). MSC: 82B10 82B20 PDFBibTeX XMLCite \textit{S.-J. Li} et al., Int. J. Numer. Model. 20, No. 3, 109--116 (2007; Zbl 1241.82013) Full Text: DOI
Chang, Chia-Cherng; Li, Szu-Ju; Tsai, Yao-Tsung An equivalent-circuit modelling on vertical and horizontal integrations for MOS flat-band voltage simulation. (English) Zbl 1089.78508 Int. J. Numer. Model. 19, No. 3, 289-300 (2006). MSC: 78M20 PDFBibTeX XMLCite \textit{C.-C. Chang} et al., Int. J. Numer. Model. 19, No. 3, 289--300 (2006; Zbl 1089.78508) Full Text: DOI
Li, Szu-Ju; Chang, Chia-Cherng; Tsai, Yao-Tsung Simulation of Si \(n\)-MOS inversion layer with Schrödinger-Poisson equivalent circuit model. (English) Zbl 1145.81358 Int. J. Numer. Model. 19, No. 3, 229-238 (2006). MSC: 81Q05 94C05 PDFBibTeX XMLCite \textit{S.-J. Li} et al., Int. J. Numer. Model. 19, No. 3, 229--238 (2006; Zbl 1145.81358) Full Text: DOI
Chang, Chia-Cherng; Li, Szu-Ju; Tsai, Yao-Tsung Device-partition method using equivalent circuit model in two-dimensional device simulation. (English) Zbl 1154.78321 Int. J. Numer. Model. 18, No. 3, 203-219 (2005). MSC: 78M25 94C05 PDFBibTeX XMLCite \textit{C.-C. Chang} et al., Int. J. Numer. Model. 18, No. 3, 203--219 (2005; Zbl 1154.78321) Full Text: DOI
Dai, Jing-Fu; Chang, Chia-Cherng; Lee, Jia-Wen; Li, Szu-Ju; Tsai, Yao-Tsung Simplified equivalent-circuit modelling for decoupled and partial decoupled methods in semiconductor device simulation. (English) Zbl 1161.82368 Int. J. Numer. Model. 17, No. 5, 421-432 (2004). Reviewer: Andreas Knorr (Berlin) MSC: 82D37 PDFBibTeX XMLCite \textit{J.-F. Dai} et al., Int. J. Numer. Model. 17, No. 5, 421--432 (2004; Zbl 1161.82368) Full Text: DOI
Chang, Chia-Cherng; Dai, Jing-Fu; Tsai, Yao-Tsung Verification of 1D BJT numerical simulation and its application to mixed-level device and circuit simulation. (English) Zbl 1035.82503 Int. J. Numer. Model. 16, No. 1, 81-94 (2003). MSC: 82D37 PDFBibTeX XMLCite \textit{C.-C. Chang} et al., Int. J. Numer. Model. 16, No. 1, 81--94 (2003; Zbl 1035.82503) Full Text: DOI
Tsai, Yao-Tsung; Ke, Tien-Chi Electrode separation method to the boundary condition for a-Si TFT mixed-level simulation. (English) Zbl 0909.65126 Int. J. Numer. Model. 11, No. 2, 123-130 (1998). Reviewer: P.K.Mahanti (Ranchi) MSC: 65Z05 35Q60 78A55 PDFBibTeX XMLCite \textit{Y.-T. Tsai} and \textit{T.-C. Ke}, Int. J. Numer. Model. 11, No. 2, 123--130 (1998; Zbl 0909.65126) Full Text: DOI