Inaba, Motoi; Shen, Jing; Tanno, Koichi; Ishizuka, Okihiko Voltage-mode variable threshold circuits with neuron MOS transistors for multi-valued logic. (English) Zbl 1032.94535 Mult.-Valued Log. 8, No. 1, 89-126 (2002). MSC: 94C05 94C10 PDFBibTeX XMLCite \textit{M. Inaba} et al., Mult.-Valued Log. 8, No. 1, 89--126 (2002; Zbl 1032.94535)
Kaeriyama, Shunichi; Hanyu, Takahiro; Kameyama, Michitaka Arithmetic-oriented logic-in-memory VLSI using floating-gate MOS transistors. (English) Zbl 1032.94539 Mult.-Valued Log. 8, No. 1, 33-51 (2002). MSC: 94C10 94C05 PDFBibTeX XMLCite \textit{S. Kaeriyama} et al., Mult.-Valued Log. 8, No. 1, 33--51 (2002; Zbl 1032.94539)
Waho, Takao; Hattori, Kazufumi; Honda, Kouji Ultrahigh-speed multiple-threshold comparator using resonant-tunneling diodes and heterojunction FETs. (English) Zbl 1032.94536 Mult.-Valued Log. 8, No. 1, 17-31 (2002). MSC: 94C05 94C10 PDFBibTeX XMLCite \textit{T. Waho} et al., Mult.-Valued Log. 8, No. 1, 17--31 (2002; Zbl 1032.94536)
Olson, Dan; Current, K. Wayne Demonstration of “supplementary symmetrical logig circuit structure” concepts using a MOS test chip. (English) Zbl 1013.94551 Mult.-Valued Log. 7, No. 1-2, 1-23 (2001). MSC: 94C10 94C05 PDFBibTeX XMLCite \textit{D. Olson} and \textit{K. W. Current}, Mult.-Valued Log. 7, No. 1--2, 1--23 (2001; Zbl 1013.94551)
Nozaki, Akihiro Completeness of unit-delay functions based on sequential circuits. (English) Zbl 1013.94044 Mult.-Valued Log. 7, No. 5-6, 295-312 (2001). MSC: 94C10 03B50 94C05 PDFBibTeX XMLCite \textit{A. Nozaki}, Mult.-Valued Log. 7, No. 5--6, 295--312 (2001; Zbl 1013.94044)
Hang, Guoqiang; Wu, Xunwei Current threshold-controllable technique and ternary current-mode CMOS Schmitt circuits. (English) Zbl 1011.94032 Mult.-Valued Log. 7, No. 3-4, 283-294 (2001). MSC: 94C05 94C10 PDFBibTeX XMLCite \textit{G. Hang} and \textit{X. Wu}, Mult.-Valued Log. 7, No. 3--4, 283--294 (2001; Zbl 1011.94032)
Wang, Guo-Jun Antichains and its application to enumerating regular ternary logic functions. (English) Zbl 1003.03524 Mult.-Valued Log. 7, No. 3-4, 259-267 (2001). MSC: 03B50 94C10 06A07 PDFBibTeX XMLCite \textit{G.-J. Wang}, Mult.-Valued Log. 7, No. 3--4, 259--267 (2001; Zbl 1003.03524)
Wu, Xunwei; Chen, Bangyuan; Pedram, Massoud Power estimation in binary CMOS circuits based on multiple-valued logic. (English) Zbl 1011.94034 Mult.-Valued Log. 7, No. 3-4, 195-211 (2001). MSC: 94C05 94C10 PDFBibTeX XMLCite \textit{X. Wu} et al., Mult.-Valued Log. 7, No. 3--4, 195--211 (2001; Zbl 1011.94034)
Stanković, Radomir S. Matrix-valued EXOR-TDDs in decomposition of switching functions. (English) Zbl 1019.94039 Mult.-Valued Log. 7, No. 1-2, 163-180 (2001). Reviewer: A. V. Chashkin (Moskva) MSC: 94C10 PDFBibTeX XMLCite \textit{R. S. Stanković}, Mult.-Valued Log. 7, No. 1--2, 163--180 (2001; Zbl 1019.94039)
Cortés-Rodríguez, F.; Muñoz-Rodríguez, D.; Soto, R.; Maturino, H. Multi-valued logic application for a cellular handoff algorithm. (English) Zbl 1016.94002 Mult.-Valued Log. 7, No. 1-2, 75-95 (2001). Reviewer: Radko Mesiar (Bratislava) MSC: 94A05 68U20 94D05 03B50 PDFBibTeX XMLCite \textit{F. Cortés-Rodríguez} et al., Mult.-Valued Log. 7, No. 1--2, 75--95 (2001; Zbl 1016.94002)
Drechsler, Rolf; Keim, Martin; Becker, Bernd Fault simulation in multi-valued logic networks. (English) Zbl 1015.94554 Mult.-Valued Log. 7, No. 1-2, 25-47 (2001). MSC: 94C12 68U20 PDFBibTeX XMLCite \textit{R. Drechsler} et al., Mult.-Valued Log. 7, No. 1--2, 25--47 (2001; Zbl 1015.94554)
Krone, Joan; Westmoreland, Michael Collision models for multiple-valued logic gates. (English) Zbl 1014.94032 Mult.-Valued Log. 6, No. 5-6, 405-421 (2001). MSC: 94C10 03B50 81P10 PDFBibTeX XMLCite \textit{J. Krone} and \textit{M. Westmoreland}, Mult.-Valued Log. 6, No. 5--6, 405--421 (2001; Zbl 1014.94032)
Thoidis, I. M.; Soudris, D.; Karafyllidis, I.; Thanailakis, A. Design of novel multiple-valued logic voltage-mode storage circuits. (English) Zbl 1007.68003 Mult.-Valued Log. 6, No. 3-4, 345-367 (2001). MSC: 68M07 94C05 PDFBibTeX XMLCite \textit{I. M. Thoidis} et al., Mult.-Valued Log. 6, No. 3--4, 345--367 (2001; Zbl 1007.68003)
Tomescu, Ioan A cascade version of Dantzig’s inductive algorithm for matrices over semilattice-ordered semigroups. (English) Zbl 1050.68169 Mult.-Valued Log. 6, No. 1-2, 217-228 (2001). MSC: 68W05 05C85 68R10 94C15 06F05 PDFBibTeX XMLCite \textit{I. Tomescu}, Mult.-Valued Log. 6, No. 1--2, 217--228 (2001; Zbl 1050.68169)
Kalay, Ugur; Hall, Douglas V.; Perkowski, Marek A. Easily testable multiple-valued Galois field sum-of-products circuits. (English) Zbl 1003.94541 Mult.-Valued Log. 5, No. 6, 507-528 (2000). MSC: 94C10 94C12 PDFBibTeX XMLCite \textit{U. Kalay} et al., Mult.-Valued Log. 5, No. 6, 507--528 (2000; Zbl 1003.94541)
Takanami, Itsuo A note on realizing multiple-valued logic functions using Akers’ cells – array sizes and path lengths. (English) Zbl 1001.94523 Mult.-Valued Log. 5, No. 6, 489-505 (2000). MSC: 94C10 68M07 PDFBibTeX XMLCite \textit{I. Takanami}, Mult.-Valued Log. 5, No. 6, 489--505 (2000; Zbl 1001.94523)
Herrfeld, A.; Hentschke, S. A ternary flip-flop for dynamic double-rail circuits. (English) Zbl 0956.94029 Mult.-Valued Log. 5, No. 1, 39-44 (2000). MSC: 94C10 PDFBibTeX XMLCite \textit{A. Herrfeld} and \textit{S. Hentschke}, Mult.-Valued Log. 5, No. 1, 39--44 (2000; Zbl 0956.94029)
Picton, P. D. A universal architecture for multiple-valued reversible logic. (English) Zbl 0956.94032 Mult.-Valued Log. 5, No. 1, 27-37 (2000). MSC: 94C10 PDFBibTeX XMLCite \textit{P. D. Picton}, Mult.-Valued Log. 5, No. 1, 27--37 (2000; Zbl 0956.94032)
Chang, Yeong-Jar; Lee, Chung Len; Chen, Jwu E Fault models for multi-valued current mode CMOS circuits. (English) Zbl 0956.94033 Mult.-Valued Log. 5, No. 1, 15-25 (2000). MSC: 94C12 PDFBibTeX XMLCite \textit{Y.-J. Chang} et al., Mult.-Valued Log. 5, No. 1, 15--25 (2000; Zbl 0956.94033)
Muranaka, Noriaki; Murayama, Testuya; Imanishi, Shigeru; Miller, D. Michael A quaternary systolic product-sum finite field computation circuit using neuron MOSFETs. (English) Zbl 0956.94031 Mult.-Valued Log. 4, No. 4, 307-327 (1999). MSC: 94C10 PDFBibTeX XMLCite \textit{N. Muranaka} et al., Mult.-Valued Log. 4, No. 4, 307--327 (1999; Zbl 0956.94031)
Kamiura, Naotake; Hata, Yutaka; Yamato, Kazuharu Fail-safe ternary cellular arrays designed from binary decision diagrams. (English) Zbl 0956.94030 Mult.-Valued Log. 4, No. 4, 267-279 (1999). MSC: 94C10 PDFBibTeX XMLCite \textit{N. Kamiura} et al., Mult.-Valued Log. 4, No. 4, 267--279 (1999; Zbl 0956.94030)
Takagi, Noboru; Nakashima, Kyoichi; Mukaidono, Masao Explicit representation of many-valued Łukasiewicz logic functions. (English) Zbl 0965.03034 Mult.-Valued Log. 4, No. 4, 249-266 (1999). Reviewer: A.Karpenko (Moskva) MSC: 03B50 94C10 94D05 PDFBibTeX XMLCite \textit{N. Takagi} et al., Mult.-Valued Log. 4, No. 4, 249--266 (1999; Zbl 0965.03034)
Yuminaka, Yasushi; Aoki, Takafumi; Higuchi, Tatsuo Frequency-mode set-valued logic for wave-parallel computing – design and experimental realization. (English) Zbl 0988.94041 Mult.-Valued Log. 3, No. 4, 301-332 (1998). MSC: 94C10 68W10 PDFBibTeX XMLCite \textit{Y. Yuminaka} et al., Mult.-Valued Log. 3, No. 4, 301--332 (1998; Zbl 0988.94041)
Ubar, Raimund Multi-valued simulation of digital circuits with structurally synthesized binary decision diagrams. (English) Zbl 1025.94513 Mult.-Valued Log. 4, No. 1-2, 141-157 (1998). MSC: 94C10 94C12 PDFBibTeX XMLCite \textit{R. Ubar}, Mult.-Valued Log. 4, No. 1--2, 141--157 (1998; Zbl 1025.94513)
Sieling, Detlef; Wegener, Ingo On the representation of partially symmetric Boolean functions by ordered multiple valued decision diagrams. (English) Zbl 1025.94516 Mult.-Valued Log. 4, No. 1-2, 63-96 (1998). MSC: 94C10 06E30 94C15 PDFBibTeX XMLCite \textit{D. Sieling} and \textit{I. Wegener}, Mult.-Valued Log. 4, No. 1--2, 63--96 (1998; Zbl 1025.94516)
Kam, Timothy; Villa, Tiziano; Brayton, Robert K.; Sangiovanni-Vincentelli, Alberto L. Multi-valued decision diagrams: Theory and applications. (English) Zbl 1025.94515 Mult.-Valued Log. 4, No. 1-2, 9-62 (1998). MSC: 94C10 90C27 05C85 94C15 PDFBibTeX XMLCite \textit{T. Kam} et al., Mult.-Valued Log. 4, No. 1--2, 9--62 (1998; Zbl 1025.94515)
Drechsler, Rolf; Miller, D. Michael Decision diagrams in multi-valued logic. (English) Zbl 1025.94514 Mult.-Valued Log. 4, No. 1-2, 1-8 (1998). MSC: 94C10 94-02 PDFBibTeX XMLCite \textit{R. Drechsler} and \textit{D. M. Miller}, Mult.-Valued Log. 4, No. 1--2, 1--8 (1998; Zbl 1025.94514)
Stanković, Radomir S. Functional decision diagrams for multiple-valued functions. (English) Zbl 0920.94017 Mult.-Valued Log. 3, No. 3, 195-215 (1998). Reviewer: H.Salum (Tallinn) MSC: 94C10 12F99 PDFBibTeX XMLCite \textit{R. S. Stanković}, Mult.-Valued Log. 3, No. 3, 195--215 (1998; Zbl 0920.94017)
Green, D. H. Multiple-valued Reed-Muller expansions with disjoint product terms. (English) Zbl 0899.94030 Mult.-Valued Log. 3, No. 2, 111-134 (1998). Reviewer: I.Strazdins (Riga) MSC: 94C10 94A55 PDFBibTeX XMLCite \textit{D. H. Green}, Mult.-Valued Log. 3, No. 2, 111--134 (1998; Zbl 0899.94030)
Hozumi, Takahiro; Hata, Yutaka; Kamiura, Naotake; Yamato, Kazuharu Multiple-valued logic design based on gate model networks. (English) Zbl 0961.94019 Mult.-Valued Log. 3, No. 1, 1-20 (1998). MSC: 94C10 68T05 92B20 PDFBibTeX XMLCite \textit{T. Hozumi} et al., Mult.-Valued Log. 3, No. 1, 1--20 (1998; Zbl 0961.94019)
Takagi, Noboru; Nakamura, Yutaka; Nakashima, Kyoichi Set-valued logic functions monotonic in the set-theoretical inclusion. (English) Zbl 0887.94017 Mult.-Valued Log. 2, No. 4, 287-304 (1997). Reviewer: S.Rudeanu (Bucureşti) MSC: 94C10 03B50 06E30 PDFBibTeX XMLCite \textit{N. Takagi} et al., Mult.-Valued Log. 2, No. 4, 287--304 (1997; Zbl 0887.94017)
Moraga, Claudio; Oenning, Ralph; Karpovsky, Mark The Zhang-Watari transform: A discrete, real-valued, generalized Haar transform. (English) Zbl 0874.94048 Mult.-Valued Log. 2, No. 3, 245-262 (1997). MSC: 94C10 PDFBibTeX XMLCite \textit{C. Moraga} et al., Mult.-Valued Log. 2, No. 3, 245--262 (1997; Zbl 0874.94048)
Zilic, Zeljko; Vranesic, Zvonko G. Polynomial interpolation for Reed-Muller forms for incompletely specified functions. (English) Zbl 0874.94049 Mult.-Valued Log. 2, No. 3, 217-243 (1997). MSC: 94C10 PDFBibTeX XMLCite \textit{Z. Zilic} and \textit{Z. G. Vranesic}, Mult.-Valued Log. 2, No. 3, 217--243 (1997; Zbl 0874.94049)
Ngom, Alioune; Reischer, Corina; Simovici, Dan A.; Stojmenovic, Ivan Set-valued logic algebra: A carrier computing foundation. (English) Zbl 0882.03020 Mult.-Valued Log. 2, No. 3, 183-216 (1997). Reviewer: J.Henno (Tallinn) MSC: 03B50 94C10 PDFBibTeX XMLCite \textit{A. Ngom} et al., Mult.-Valued Log. 2, No. 3, 183--216 (1997; Zbl 0882.03020)
Hozumi, Takahiro; Kamiura, Naotake; Hata, Yutaka; Yamato, Kazuharu On minimization of multiple-valued sum-of-products expression with multiple-valued TRSUM. (English) Zbl 0873.94037 Mult.-Valued Log. 2, No. 2, 141-158 (1997). MSC: 94C10 PDFBibTeX XMLCite \textit{T. Hozumi} et al., Mult.-Valued Log. 2, No. 2, 141--158 (1997; Zbl 0873.94037)
Nagata, Yasunori; Mukaidono, Masao A method of test pattern generation for multiple-valued PLAs. (English) Zbl 0876.94058 Mult.-Valued Log. 2, No. 2, 127-140 (1997). MSC: 94C10 PDFBibTeX XMLCite \textit{Y. Nagata} and \textit{M. Mukaidono}, Mult.-Valued Log. 2, No. 2, 127--140 (1997; Zbl 0876.94058)
Ishizuka, O.; Handoko, D.; Tanno, K.; Tang, Z.; McCluskey, E. J. Circuit design of a multi-valued carry look-ahead adder. (English) Zbl 0873.94038 Mult.-Valued Log. 2, No. 2, 111-126 (1997). MSC: 94C10 PDFBibTeX XMLCite \textit{O. Ishizuka} et al., Mult.-Valued Log. 2, No. 2, 111--126 (1997; Zbl 0873.94038)
Hozumi, Takahiro; Utsumi, Takashi; Kamiura, Naotake; Hata, Yutaka; Yamato, Kazuharu Design of MIN-of-TSUM form multiple-valued PLA’s using universal literals. (English) Zbl 0874.94046 Mult.-Valued Log. 2, No. 2, 79-109 (1997). MSC: 94C10 PDFBibTeX XMLCite \textit{T. Hozumi} et al., Mult.-Valued Log. 2, No. 2, 79--109 (1997; Zbl 0874.94046)
Pogosyan, Grant; Nozaki, Akihiro Completeness and closed classes of Boolean functions under compositions with feedback loops. (English) Zbl 0867.94040 Mult.-Valued Log. 1, No. 4, 285-306 (1996). MSC: 94C10 PDFBibTeX XMLCite \textit{G. Pogosyan} and \textit{A. Nozaki}, Mult.-Valued Log. 1, No. 4, 285--306 (1996; Zbl 0867.94040)
Liu, Renren Some results on the decision for Sheffer functions in partial \(k\)-valued logic. (English) Zbl 0877.94063 Mult.-Valued Log. 1, No. 4, 253-269 (1996). Reviewer: J.Hromkovič (Aachen) MSC: 94C10 03B50 PDFBibTeX XMLCite \textit{R. Liu}, Mult.-Valued Log. 1, No. 4, 253--269 (1996; Zbl 0877.94063)
Picton, P. D. Multi-valued sequential logic design using Fredkin gates. (English) Zbl 0865.94034 Mult.-Valued Log. 1, No. 4, 241-251 (1996). MSC: 94C10 PDFBibTeX XMLCite \textit{P. D. Picton}, Mult.-Valued Log. 1, No. 4, 241--251 (1996; Zbl 0865.94034)
Denecke, K. The entropy sequence of unary logical functions. (English) Zbl 0874.94045 Mult.-Valued Log. 2, No. 1, 59-66 (1996). MSC: 94C10 08A40 PDFBibTeX XMLCite \textit{K. Denecke}, Mult.-Valued Log. 2, No. 1, 59--66 (1996; Zbl 0874.94045)
Wang, Hui Min; Lee, Chung Len; Chen, Jwu E. Complete test set generation for multiple-valued logic networks. (English) Zbl 0903.94063 Mult.-Valued Log. 1, No. 3, 185-218 (1996). MSC: 94C12 94C10 PDFBibTeX XMLCite \textit{H. M. Wang} et al., Mult.-Valued Log. 1, No. 3, 185--218 (1996; Zbl 0903.94063)
Deng, Xiaowei; Hanyu, Takahiro; Kameyama, Michitaka Synthesis of multiple-valued logic networks based on super pass gates. (English) Zbl 0903.94061 Mult.-Valued Log. 1, No. 3, 161-183 (1996). MSC: 94C10 PDFBibTeX XMLCite \textit{X. Deng} et al., Mult.-Valued Log. 1, No. 3, 161--183 (1996; Zbl 0903.94061)
Epstein, G.; Prentice, R. W.; Razavi, H. M.; Spring, E. N. Optimal codings for binary-coded quaternary adders. (English) Zbl 0902.94034 Mult.-Valued Log. 1, No. 2, 143-159 (1996). MSC: 94C10 68M07 94A29 94B60 PDFBibTeX XMLCite \textit{G. Epstein} et al., Mult.-Valued Log. 1, No. 2, 143--159 (1996; Zbl 0902.94034)
Zivkovic, Dejan A note on computing the OR and AND gate by a probabilistic depth-2 circuit. (English) Zbl 0895.94014 Mult.-Valued Log. 1, No. 2, 135-141 (1996). MSC: 94C10 PDFBibTeX XMLCite \textit{D. Zivkovic}, Mult.-Valued Log. 1, No. 2, 135--141 (1996; Zbl 0895.94014)
Dubrova, E. V.; Muzio, J. C. Generalized Reed-Muller canonical form for a multiple-valued algebra. (English) Zbl 1053.94587 Mult.-Valued Log. 1, No. 1, 65-84 (1996). MSC: 94C10 PDFBibTeX XMLCite \textit{E. V. Dubrova} and \textit{J. C. Muzio}, Mult.-Valued Log. 1, No. 1, 65--84 (1996; Zbl 1053.94587)
Sasao, Tsutomu; Butler, Jon T. Planar decision diagrams for multiple-valued functions. (English) Zbl 0904.94031 Mult.-Valued Log. 1, No. 1, 39-64 (1996). Reviewer: I.Strazdins (Riga) MSC: 94C10 68R10 94C15 PDFBibTeX XMLCite \textit{T. Sasao} and \textit{J. T. Butler}, Mult.-Valued Log. 1, No. 1, 39--64 (1996; Zbl 0904.94031)
Zadeh, Lotfi A. Fuzzy logic and the calculi of fuzzy rules and fuzzy graphs: A precis. (English) Zbl 0906.03022 Mult.-Valued Log. 1, No. 1, 1-38 (1996). Reviewer: S.Gottwald (Leipzig) MSC: 03B52 68T27 94D05 PDFBibTeX XMLCite \textit{L. A. Zadeh}, Mult.-Valued Log. 1, No. 1, 1--38 (1996; Zbl 0906.03022)