Dvorak, Vaclav Design and microprogramming of bit-sequential processors for parallel systems. (English) Zbl 0638.68008 J. Inf. Process. Cybern. 23, 587-597 (1987). A bit-sequential processing element (PE) of an \(N\times N\) array with bit stack architecture is presented that is simpler and more flexible than the processors in use. A microprogramming technique developed for this type of PEs is based on iterative decomposition of Boolean functions. The technique makes possible an efficient implementation of the given set of operations, i.e. a set of combinational and sequential transformations on the PE. In the process of synthesis the microprogram itself as well as a minimum set of microoperations are derived simultaneously. Applications of the PE and its microprogramming technique are expected in cellular automata, VLSI bit-sequential processor arrays, iterative arrays of logical circuits, and the like. MSC: 68N99 Theory of software 68N25 Theory of operating systems Keywords:parallel computing systems; bit-sequential processing element; microprogramming; decomposition of Boolean functions PDFBibTeX XMLCite \textit{V. Dvorak}, J. Inf. Process. Cybern. 23, 587--597 (1987; Zbl 0638.68008)