Wang, Xinsheng; Yu, Mingyan; Wang, Chenxu Structure-preserving-based model-order reduction of parameterized interconnect systems. (English) Zbl 1426.94175 Circuits Syst. Signal Process. 37, No. 1, 19-48 (2018). MSC: 94C05 PDFBibTeX XMLCite \textit{X. Wang} et al., Circuits Syst. Signal Process. 37, No. 1, 19--48 (2018; Zbl 1426.94175) Full Text: DOI
Wang, Xiao Yuan; Iu, Herbert H. C.; Wang, Guang Yi; Liu, Wei Study on time domain characteristics of memristive RLC series circuits. (English) Zbl 1364.94796 Circuits Syst. Signal Process. 35, No. 11, 4129-4138 (2016). MSC: 94C05 PDFBibTeX XMLCite \textit{X. Y. Wang} et al., Circuits Syst. Signal Process. 35, No. 11, 4129--4138 (2016; Zbl 1364.94796) Full Text: DOI