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Diagnosis of interconnects using a structured walking-1 approach. (English) Zbl 0875.68028
Summary: This paper presents a new approach for testing interconnects for boundary scan architectures. This approach relies on a structured walking-1 test set in the sense that a structural analysis based on the layout of the interconnect, is carried out. The proposed structural test method differs from previous approaches as it explicitly avoids aliasing and confounding and is applicable to dense as well as sparse interconnect layouts. The proposed method is applicable to both one-step and two-step test generation and diagnosis of stuck-at as well as bridge faults. Two algorithms with an execution complexity of \(O(n^{2})\), where n is the number of nets in the interconnect, are given. New criteria for test vector compaction are proposed; a greedy condition is exploited to compact test vectors for one-step and two-step diagnosis. For a given interconnect, the two-step diagnosis algorithm requires a number of tests as a function of the number of faults present, while the one-step algorithm requires a fixed number of tests. Simulation results for benchmark and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches compared with previous approaches. It is also shown that the proposed algorithms can be used interchangeably depending on the requirements of the overall test process (such as off/on-line execution as well as reduction in number of vectors and test generation time).
MSC:
68M07 Mathematical problems of computer architecture
94C12 Fault detection; testing in circuits and networks
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