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Counting the number of fault patterns in redundant VLSI arrays. (English) Zbl 0796.94022
Summary: In VLSI technology, redundancy is a commonly adopted technique to provide reconfiguration capabilities to regular architectures. This paper proves upper and lower bounds on the number of minimal fault patterns (minimal set of faulty processors) which affect a link-redundant linear array in an unrepairable way, for both the cases of bidirectional and unidirectional links.

MSC:
94C12 Fault detection; testing in circuits and networks
68M20 Performance evaluation, queueing, and scheduling in the context of computer systems
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