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**On regional optimization of grid and relaxation parameter for finite difference solution of Poisson’s equation in reverse biased planar type p-n junctions.**
*(English)*
Zbl 0703.65056

Authors’ summary: The optimization of grid structure and relaxation parameter is considered in connection with two-dimensional finite difference solution of Poisson’s equation for determining the field profile in a reverse biased planar type p-n junction. By dividing the planar junction into regions with rectangular and circular symmetry, regional optimizations are carried out using small area test sites. Having obtained the optimal grid size and relaxation parameter for each region, the complete solution is obtained easily with very fast convergences. The method involved in this kind of regional optimization is presented in detail with discussions on its comparative usefulness with other known techniques.

Reviewer: C.L.Koul

### MSC:

65N22 | Numerical solution of discretized equations for boundary value problems involving PDEs |

65N50 | Mesh generation, refinement, and adaptive methods for boundary value problems involving PDEs |

65F10 | Iterative numerical methods for linear systems |

65N15 | Error bounds for boundary value problems involving PDEs |

65N06 | Finite difference methods for boundary value problems involving PDEs |

35Q60 | PDEs in connection with optics and electromagnetic theory |

35J05 | Laplace operator, Helmholtz equation (reduced wave equation), Poisson equation |

78A55 | Technical applications of optics and electromagnetic theory |

### Keywords:

reverse bias; semiconductor transport equations; grid structure; relaxation parameter; finite difference solution; Poisson’s equation; fast convergences
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\textit{J. Akhtar} and \textit{S. Ahmad}, COMPEL 8, No. 4, 185--197 (1989; Zbl 0703.65056)

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### References:

[1] | DOI: 10.1109/T-ED.1984.21675 |

[2] | DOI: 10.1109/T-ED.1980.19956 |

[3] | S. Ahmad, J.P. Pachauri and J. Akhtar, Study of Current Transport in 3-D Around Submicron Size Metal Contact on Semiconductor, Technical Report, CEERI, Pilani, India (1985). |

[4] | Kurata M., Numerical Analysis of Semiconductor Devices (1982) |

[5] | Young D.M., Survey of Numerical Analysis (1962) |

[6] | DOI: 10.1007/978-3-7091-3678-2 |

[7] | DOI: 10.1007/978-3-7091-3678-2 |

[8] | DOI: 10.1049/el:19720306 |

[9] | DOI: 10.1049/el:19710251 |

[10] | S. Ahmad and J. Akhtar, Computation of Fringe Capacitance Associated with MOS Capacitor, Technical Report CEERI, Pilani, India (1986). |

[11] | DOI: 10.1109/T-ED.1977.18688 |

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