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Buying AES design resistance with speed and energy. (English) Zbl 1405.94098

Ryan, Peter Y. A. (ed.) et al., The new codebreakers. Essays dedicated to David Kahn on the occasion of his 85th birthday. Berlin: Springer (ISBN 978-3-662-49300-7/pbk; 978-3-662-49301-4/ebook). Lecture Notes in Computer Science 9100, 134-147 (2016).
Summary: Fault and power attacks are two common ways of extracting secrets from tamper-resistant chips. Although several protections have been proposed to thwart these attacks, resistant designs usually claim significant area or speed overheads. Furthermore, circuit-level countermeasures are usually not reconfigurable at runtime. This paper exploits the AES’ algorithmic features to propose low-cost and low-latency protections. We provide Verilog and FPGA implementation details. Using our design, real-life applications can be configured during runtime to meet the user’s needs and the system’s constraints.
For the entire collection see [Zbl 1334.94030].

MSC:

94A60 Cryptography
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References:

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