Greene, Jonathan W.; El Gamal, Abbas Configuation of VLSI arrays in the presence of defects. (English) Zbl 0632.94033 J. Assoc. Comput. Mach. 31, 694-717 (1984). Cited in 6 Documents MSC: 94C15 Applications of graph theory to circuits and networks 94C10 Switching theory, application of Boolean algebra; Boolean functions (MSC2010) 68M20 Performance evaluation, queueing, and scheduling in the context of computer systems Keywords:VLSI arrays; circuit area; fault tolerance; percolation theory; probabilistic analysis; queuing processes; systolic arrays; wafer-scale integration; wire length PDFBibTeX XMLCite \textit{J. W. Greene} and \textit{A. El Gamal}, J. Assoc. Comput. Mach. 31, 694--717 (1984; Zbl 0632.94033) Full Text: DOI