Bhattacharyya, Shuvra S. (ed.); Deprettere, Ed F. (ed.); Leupers, Rainer (ed.); Takala, Jatmo (ed.) Handbook of signal processing systems. Foreword by S. Y. Kung. (English) Zbl 1285.94001 New York, NY: Springer (ISBN 978-1-4419-6344-4/hbk; 978-1-4419-6345-1/ebook). xxxviii, 1083 p. (2010). MSC: 94-00 94-06 94A12 00B15 PDFBibTeX XMLCite \textit{S. S. Bhattacharyya} (ed.) et al., Handbook of signal processing systems. Foreword by S. Y. Kung. New York, NY: Springer (2010; Zbl 1285.94001) Full Text: DOI
Ko, Ming-Yung; Zissulescu, Claudiu; Puthenpurayil, Sebastian; Bhattacharyya, Shuvra S.; Kienhuis, Bart; Deprettere, Ed F. Parameterized looped schedules for compact representation of execution sequences in DSP hardware and software implementation. (English) Zbl 1391.94274 IEEE Trans. Signal Process. 55, No. 6, Part 2, 3126-3138 (2007). MSC: 94A12 68N30 PDFBibTeX XMLCite \textit{M.-Y. Ko} et al., IEEE Trans. Signal Process. 55, No. 6, Part 2, 3126--3138 (2007; Zbl 1391.94274) Full Text: DOI
Lemma, Aweke N.; van der Veen, Alle-Jan; Deprettere, Ed F. Analysis of joint angle-frequency estimation using ESPRIT. (English) Zbl 1369.94202 IEEE Trans. Signal Process. 51, No. 5, 1264-1283 (2003). MSC: 94A12 PDFBibTeX XMLCite \textit{A. N. Lemma} et al., IEEE Trans. Signal Process. 51, No. 5, 1264--1283 (2003; Zbl 1369.94202) Full Text: DOI
Lieverse, Paul; Van der Wolf, Pieter; Vissers, Kees; Deprettere, Ed A methodology for architecture exploration of heterogeneous signal processing systems. (English) Zbl 0996.68594 J. VLSI Signal Process. Syst. Signal Image Video Technol. 29, No. 3, 197-207 (2001). MSC: 68U99 94A12 68M99 PDFBibTeX XMLCite \textit{P. Lieverse} et al., J. VLSI Signal Process. Syst. Signal Image Video Technol. 29, No. 3, 197--207 (2001; Zbl 0996.68594) Full Text: DOI
Moonen, Marc; Deprettere, Ed A fully pipelined RLS-based array for channel equalization. (English) Zbl 0862.94004 J. VLSI Signal Process. 14, No. 1, 67-74 (1996). MSC: 94A12 93E24 68W10 PDFBibTeX XMLCite \textit{M. Moonen} and \textit{E. Deprettere}, J. VLSI Signal Process. 14, No. 1, 67--74 (1996; Zbl 0862.94004) Full Text: DOI
Nelis, Harry W.; Deprettere, Ed F. Automatic design and partitioning of systolic/wavefront arrays for VLSI. (English) Zbl 0647.68027 Circuits Syst. Signal Process. 7, No. 2, 235-252 (1988). MSC: 68N25 94C10 68Q80 PDFBibTeX XMLCite \textit{H. W. Nelis} and \textit{E. F. Deprettere}, Circuits Syst. Signal Process. 7, No. 2, 235--252 (1988; Zbl 0647.68027) Full Text: DOI
Deprettere, Ed F. A.; Jainandunsing, Kishan An efficient VLSI solver for a special set of near Toeplitz systems of equations. (English) Zbl 0633.68020 Computational and combinatorial methods in systems theory, Sel. Pap. 7th Int. Symp. Math. Theory Networks Syst., Stockholm 1985, 397-407 (1986). MSC: 68W30 65F10 68T10 94A29 PDFBibTeX XML
Deprettere, E.; Dewilde, Patrick Orthogonal cascade realization of real multiport digital filters. (English) Zbl 0446.94017 Int. J. Circuit Theory Appl. 8, 245-272 (1980). MSC: 94C05 93E11 PDFBibTeX XMLCite \textit{E. Deprettere} and \textit{P. Dewilde}, Int. J. Circuit Theory Appl. 8, 245--272 (1980; Zbl 0446.94017) Full Text: DOI
Deprettere, E. A numerical calculus for constructing approximating covariance prediction/modeling filters in the time domain. (English) Zbl 0446.94016 Circuit theory and design, Proc. Eur. Conf., Lausanne 1978, 283-288 (1978). MSC: 94C05 94-04 93E11 93E25 PDFBibTeX XML
Deprettere, E. On the minimal realization of the gyrator by means of nullors and resistors. II. (English) Zbl 0338.94018 Int. J. Circuit Theory Appl. 4, 285-297 (1976). MSC: 94C10 PDFBibTeX XMLCite \textit{E. Deprettere}, Int. J. Circuit Theory Appl. 4, 285--297 (1976; Zbl 0338.94018) Full Text: DOI
Deprettere, E. On the minimal realization of the gyrator by means of nullors and resistors. (English) Zbl 0315.94027 Int. J. Circuit Theory Appl. 3, 383-390 (1975). MSC: 94C10 PDFBibTeX XMLCite \textit{E. Deprettere}, Int. J. Circuit Theory Appl. 3, 383--390 (1975; Zbl 0315.94027) Full Text: DOI